The present invention relates to a digital subscriber loop system, and more particularly to a sampling phase extracting circuit for use in a digital subscriber loop system.
A digital subscriber loop system for bidirectional communication according to the prior art is provided with an echo canceller for eliminating echo signals from the transmitter on the terminal and with an equalizer for equalizing intersymbol interference.
A conventional sampling phase extracting circuit includes a multiplier for generating a correlation signal between a residual intersymbol interference (which is the difference signal between the input signal and the output signal of the decision circuit) and the result of decision (which is the output signal of the decision circuit). The correlation signal is turned into an integrated signal resulting from N cumulative additions by an integrator. The integrated signal is sampled by a sampler at every NT to produce a sampled signal which is inputted to a phase control circuit. The phase control circuit digitally controls the phase of a baud rate clock (80 kHz), which is the operational clock for the system, for each period (about 65 nsec) of an external oscillator (15.36 MHz), which is the master clock of the system. However, the conventional phase extracting citcuit has a problem in that since it digitally controls the phase in the clock width (65 nsec) units of the master clock (15.36 MHz) in sampling phase synchronization, it invites prolongation of the phase synchronization time. This prolongation of the phase synchronization time is due to the mutual interference witnessed between the converging characteristic of the decision feedback equalizer and the synchronizing characteristic of the phase control circuit. Thus, unless the decision feedback equalizer converges, the phase control circuit will not operate normally, and the decision feedback equalizer, in order to converge, should operate within a certain limited range of phase.